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functional diagram ref 12-bit dac dac register serial register 12 clr clk sdi v dd v out gnd 12 en ld ad7390 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a +3 volt serial-input micropower 10-bit & 12-bit dacs features micropower100 m a single-supply 1 2.7 to 1 5.5 v operation compact 1.75 mm height so-8 package & 1.1 mm height tssop-8 ad739012-bit resolution ad739110-bit resolution spi & qspi serial interface compatible with schmitt trigger inputs applications automotive 0.5 v to 4.5 v output span voltage portable communications digitally controlled calibration general description the ad7390/ad7391 family of 10-bit & 12-bit voltage-output digital-to-analog converters is designed to operate from a single 1 3 v supply. built using a cbcmos process, these monolithic dacs offer the user low cost, and ease-of-use in single-supply 1 3 v systems. operation is guaranteed over the supply voltage range of 1 2.7 v to 1 5.5 v consuming less than 100 m a making this device ideal for battery operated applications. the full-scale voltage output is determined by the external ref- erence input voltage applied. the rail-to-rail ref in to dac out allows for a full-scale voltage set equal to the positive supply v dd or any value in between. a doubled-buffered serial-data interface offers high speed, three-wire, spi and microcontroller compatible inputs using data in (sdi), clock (clk) and load strobe ( ld ) pins. addi- tionally, a clr input sets the output to zero scale at power on or upon user demand. both parts are offered in the same pinout to allow users to select the amount of resolution appropriate for their application with- out circuit card redesign. the ad7390/ad7391 are specified over the extended industrial ( 2 40 c to 1 85 c) temperature range. the ad7391ar is specified for the 2 40 c to 1 125 c automotive temperature range. the ad7390/ad7391s are available in plastic dip, and low profile 1.75 mm height so-8 surface mount packages. the AD7391ARU is available for ultracompact applications in a thin 1.1 mm tssop-8 package. code ?decimal 1.00
ad7390/ad7391Cspecifications ad7390 electrical characteristics parameter symbol conditions 3 v 6 10% 5 v 6 10% units static performance resolution 1 n 12 12 bits relative accuracy 2 inl t a = 1 25 c 6 1.6 6 1.6 lsb max relative accuracy 2 inl t a = 2 40 c, 1 85 c 6 2.0 6 2 lsb max differential nonlinearity 2 dnl t a = 1 25 c, monotonic 6 0.9 6 0.9 lsb max differential nonlinearity 2 dnl monotonic 6 1 6 1 lsb max zero-scale error v zse data = 000 h 4.0 4.0 mv max full-scale voltage error v fse t a = 1 25 c, 1 85 c, data = fff h 6 8 6 8 mv max full-scale voltage error v fse t a = 2 40 c, data = fff h 6 20 6 20 mv max full-scale tempco 3 tcv fs 16 16 ppm/ c typ reference input v ref in range v ref 0/v dd 0/v dd v min/max input resistance r ref 2.5 2.5 m w typ 4 input capacitance 3 c ref 5 5 pf typ analog output output current (source) i out data = 800 h , d v out = 5 lsb 1 1 ma typ output current (sink) i out data = 800 h , d v out = 5 lsb 3 3 ma typ capacitive load 3 c l no oscillation 100 100 pf typ logic inputs logic input low voltage v il 0.5 0.8 v max logic input high voltage v ih v dd 2 0.6 v dd 2 0.6 v min input leakage current i il 10 10 m a max input capacitance 3 c il 10 10 pf max interface timing 3, 5 clock width high t ch 50 30 ns min clock width low t cl 50 30 ns min load pulse width t ldw 30 20 ns min data setup t ds 10 10 ns min data hold t dh 30 15 ns min clear pulse width t clrw 15 15 ns min load setup t ld1 30 15 ns min load hold t ld2 40 20 ns min ac characteristics 6 output slew rate sr data = 000 h to fff h to 000 h 0.05 0.05 v/ m s typ settling time t s to 6 0.1% of full scale 70 60 m s typ dac glitch q code 7ff h to 800 h to 7ff h 65 65 nvs typ digital feedthrough q 15 15 nvs typ feedthrough v out /v ref v ref = 1.5 v dc 1 1 v p-p , 2 63 2 63 db typ data = 000 h , f = 100 khz supply characteristics power supply range v dd range dnl < 6 1 lsb 2.7/5.5 2.7/5.5 v min/max positive supply current i dd v il = 0 v, no load, t a = 1 25 c55 55 m a typ positive supply current i dd v il = 0 v, no load 100 100 m a max power dissipation p diss v il = 0 v, no load 300 500 m w max power supply sensitivity pss d v dd = 6 5% 0.003 0.006 %/% max notes 1 one lsb = v ref /4096 v for the 12-bit ad7390. 2 the first two codes (000 h , 001 h ) are excluded from the linearity error measurement. 3 these parameters are guaranteed by design and not subject to production testing. 4 typicals represent average readings measured at 25 c. 5 all input control signals are specified with t r = t f = 2 ns (10% to 90% of 1 3 v) and timed from a voltage level of 1.6 v. 6 the settling time specification does not apply for negative going transitions within the last 3 lsbs of ground. specifications subject to change without notice. rev. 0 C2C (@ v ref in = 2.5 v, 2 40 8 c < t a < 1 85 8 c, unless otherwise noted)
specifications ad7391 electrical characteristics parameter symbol conditions 3 v 6 10% 5 v 6 10% units static performance resolution 1 n 10 10 bits relative accuracy 2 inl t a = 1 25 c 6 1.75 6 1.75 lsb max relative accuracy 2 inl t a = 2 40 c, 1 85 c, 1 125 c 6 2.0 6 2.0 lsb max differential nonlinearity 2 dnl monotonic 6 0.9 6 0.9 lsb max zero-scale error v zse data = 000 h 9.0 9.0 mv max full-scale voltage error v fse t a = 1 25 c, 1 85 c, 1 125 c, 6 32 6 32 mv max data = 3ff h full-scale voltage error v fse t a = 2 40 c, data = 3ff h 6 35 6 35 mv max full-scale tempco 3 tcv fs 16 16 ppm/ c typ reference input v ref in range v ref 0/v dd 0/v dd v min/max input resistance r ref 2.5 2.5 m w typ 4 input capacitance 3 c ref 5 5 pf typ analog output output current (source) i out data = 800 h , d v out = 5 lsb 1 1 ma typ output current (sink) i out data = 800 h , d v out = 5 lsb 3 3 ma typ capacitive load 3 c l no oscillation 100 100 pf typ logic inputs logic input low voltage v il 0.5 0.8 v min logic input high voltage v ih v dd 2 0.6 v dd 2 0.6 v max input leakage current i il 10 10 m a max input capacitance 3 c il 10 10 pf max interface timing 3, 5 clock width high t ch 50 30 ns clock width low t cl 50 30 ns load pulse width t ldw 30 20 ns data setup t ds 10 10 ns data hold t dh 30 15 ns clear pulse width t clrw 15 15 ns load setup t ld1 30 15 ns load hold t ld2 40 20 ns ac characteristics 6 output slew rate sr data = 000 h to 3ff h to 000 h 0.05 0.05 v/ m s typ settling time t s to 6 0.1% of full scale 70 60 m s typ dac glitch q code 7ff h to 800 h to 7ff h 65 65 nvs typ digital feedthrough q 15 15 nvs typ feedthrough v out /v ref v ref = 1.5 v dc 1 1 v p-p, 2 63 2 63 db typ data = 000 h , f = 100 khz supply characteristics power supply range v dd range dnl < 6 1 lsb 2.7/5.5 2.7/5.5 v min/max positive supply current i dd v il = 0 v, no load, t a = 1 25 c55 55 m a typ positive supply current i dd v il = 0 v, no load 100 100 m a max power dissipation p diss v il = 0 v, no load 300 500 m w max power supply sensitivity pss d v dd = 6 5% 0.003 0.006 %/% max notes 1 one lsb = v ref /1024 v for the 10-bit ad7391. 2 the first two codes (000 h , 001 h ) are excluded from the linearity error measurement. 3 these parameters are guaranteed by design and not subject to production testing. 4 typicals represent average readings measured at 25 c. 5 all input control signals are specified with t r = t f = 2 ns (10% to 90% of 1 3 v) and timed from a voltage level of 1.6 v. 6 the settling time specification does not apply for negative going transitions within the last 3 lsbs of ground. specifications subject to change without notice. (@ v ref in = 2.5 v, 2 40 8 c < t a < 1 85 8 c, unless otherwise noted) ad7390/ad7391 rev. 0 C3C
ad7390/ad7391 rev. 0 C4C warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7390/ad7391 features proprietary esd protection circuitry, permanent dam- age may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings* v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0.3 v, 1 8 v v ref to gnd . . . . . . . . . . . . . . . . . . . . . . . 0.3 v, v dd 1 0.3 v logic inputs to gnd . . . . . . . . . . . . . . . . . . . . . 2 0.3 v, 1 8 v v out to gnd . . . . . . . . . . . . . . . . . . . . . 2 0.3 v, v dd 1 0.3 v i out short circuit to gnd . . . . . . . . . . . . . . . . . . . . . . 50 ma package power dissipation . . . . . . . . . . . . . . (t j max 2 t a )/ q ja thermal resistance q ja 8-pin plastic dip package (n-8) . . . . . . . . . . . . . . 103 c/w 8-lead soic package (so-8) . . . . . . . . . . . . . . . . 158 c/w tssop-8 package (ru-8) . . . . . . . . . . . . . . . . . . . 240 c/w maximum junction temperature (t j max ) . . . . . . . . . . 150 c operating temperature range . . . . . . . . . . . 2 40 c to 1 85 c storage temperature range . . . . . . . . . . . . 2 65 c to 1 150 c lead temperature (soldering, 10 secs) . . . . . . . . . . . . 1 300 c notes *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational specification is not implied. exposure to the above maximum rating conditions for extended periods may affect device reliability. ordering guide package package model res temp description option ad7390an 12 xind 8-pin p-dip n-8 ad7390ar 12 xind 8-lead soic so-8 ad7391an 10 xind 8-pin p-dip n-8 ad7391ar 10 auto 8-lead soic so-8 AD7391ARU 10 xind tssop-8 ru-8 notes xind = 2 40 c to 1 85 c; auto = 2 40 c to 1 125 c the ad7390 contains 558 transistors. the die size measures 70 mil x 68 mil. * note: ad7391 has a 10-bit shift register clr ld clk sdi reset load dac register 12-bit ad7390* shift register d clk 12 figure 3. digital control logic pin configurations 1 2 3 4 8 7 6 top view (not to scale) so-8 5 top view (not to scale) tssop-8 1 5 2 3 4 6 7 8 1 2 3 4 8 7 6 5 top view (not to scale) ld gnd v out v dd v ref clk sdi clr p-dip-8 pin descriptions pin no. name function 1 ld load strobe. transfers shift register data to dac register while active low. see truth table for operation. 2 clk clock input. positive edge clocks data into shift register. 3 sdi serial data input. data loads directly into the shift register. 4 clr resets dac register to zero condition. active low input. 5 gnd analog & digital ground. 6v out dac voltage output. full-scale output 1 lsb less than reference input voltage ref. 7v dd positive power supply input. specified range of operation 1 2.7 v to 1 5.5 v. 8v ref dac reference input pin. establishes dac full-scale voltage.
ad7390/ad7391 rev. 0 C5C d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ld clk sdi t ld1 t ld2 t cl t ch t ds t dh sdi clk clr t ldw t clrw v out fs zs t s 0.1% fs error band t s dac register load ld t ld1 ad7390 ad7391 figure 4. timing diagram table i. control-logic truth table clk clr ld serial shift register function dac register function - h h shift-register-data advanced one-bit latched x h l disables updated with current shift register contents x l x no effect loaded with all zeros x - h no effect latched with all zeros x - l disabled previous sr contents loaded (avoid usage of clr when ld is logic low, since sr data could be corrupted if a clock edge takes place, while clr returns high.) notes 1 - = positive logic transition. 2 x = dont care. table ii. ad7390 serial input register data format, data is loaded in the msb-first format msb lsb b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ad7390 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 table iii. ad7391 serial input register data format, data is loaded in the msb-first format msb lsb b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ad7391 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
total unadjusted error ?lsb frequency 25 0 5.0 10 5 20 15 5.8 6.6 7.3 8.1 8.9 9.7 10.5 11.2 12.0 ad7390 ss = 100 units t a = 25
ad7390/ad7391 rev. 0 C7C v out ?v i out ?ma 40 30 0 01 5 23 4 20 10 v dd = +5v v ref = +3v code = h figure 14. i out at zero scale vs. v out 100? 1v time ?100?/div v out (1v/div)
ad7390/ad7391 rev. 0 C8C operation the ad7390 and ad7391 are a set of pin compatible, 12-bit/10- bit digital-to-analog converters. these single-supply operation devices consume less than 100 microamps of current while op- erating from power supplies in the 1 2.7 v to 1 5.5 v range making them ideal for battery operated applications. they con- tain a voltage-switched, 12-bit/10-bit, laser-trimmed digital-to- analog converter, rail-to-rail output op amps, serial-input register, and a dac register. the external reference input has constant input resistance independent of the digital code setting of the dac. in addition, the reference input can be tied to the same supply voltage as v dd resulting in a maximum output volt- age span of 0 to v dd . the spi compatible, serial-data interface consists of a serial data input (sdi), clock (clk), and load ( ld ) pins. a clr pin is available to reset the dac register to zero-scale. this function is useful for power-on reset or system failure recovery to a known state. d/a converter section the voltage switched r-2r dac generates an output voltage dependent on the external reference voltage connected to the v ref pin according to the following equation: equation 1 v out = v ref 2 n d 3 where d is the decimal data word loaded into the dac register, and n is the number of bits of dac resolution. in the case of the 10-bit ad7391 using a 2.5 v reference, equation 1 simplifies to: equation 2 v out = 2.5 3 1024 d using equation 2 the nominal midscale voltage at v out is 1.25 v for d = 512; full-scale voltage is 2.497 volts. the lsb step size is = 2.5 3 1/1024 = 0.0024 volts. for the 12-bit ad7390 operating from a 5.0 v reference equa- tion 1 becomes: equation 3 v out = 5.0 3 4096 d using equation 3 the ad7390 provides a nominal midscale voltage of 2.5 v for d =2048, and a full-scale output of 4.998 v. the lsb step size is = 5.0 3 1/4096 = 0.0012 volts. amplifier section the internal dacs output is buffered by a low power con- sumption precision amplifier. the op amp has a 60 m s typical settling time to 0.1% of full scale. there are slight differences in settling time for negative slewing signals versus positive. also, negative transition settling time to within the last 6 lsbs of zero volts has an extended settling time. the rail-to-rail output stage of this amplifier has been designed to provide precision perfor- mance while operating near either power supply. figure 21 shows an equivalent output schematic of the rail-to-rail ampli- fier with its n-channel pull-down fets that will pull an output load directly to gnd. the output sourcing current is provided by a p-channel pull-up device that can source current to gnd terminated loads. p-ch n-ch v dd v out agnd figure 21. equivalent analog output circuit the rail-to-rail output stage provides 6 1 ma of output current. the n-channel output pull-down mosfet shown in figure 21 has a 35 w on resistance, which sets the sink current capability near ground. in addition to resistive load driving capability, the amplifier has also been carefully designed and characterized for up to 100 pf capacitive load driving capability. reference input the reference input terminal has a constant input-resistance in- dependent of digital code which results in reduced glitches on the external reference voltage source. the high 2 m w input- resistance minimizes power dissipation within the ad7390/ ad7391 d/a converters. the v ref input accepts input voltages ranging from ground to the positive-supply voltage v dd . one of the simplest applications which saves an external reference volt- age source is connection of the v ref terminal to the positive v dd supply. this connection results in a rail-to-rail voltage out- put span maximizing the programmed range. the reference in- put will accept ac signals as long as they are kept within the supply voltage range, 0 < v ref in < v dd . the reference bandwidth and integral nonlinearity error performance are plot- ted in the typical performance section, see figures 18 and 19. the ratiometric reference feature makes the ad7390/ad7391 an ideal companion to ratiometric analog-to-digital converters such as the ad7896. power supply the very low power consumption of the ad7390/ad7391 is a di- rect result of a circuit design optimizing the use of a cbcmos process. by using the low power characteristics of cmos for the logic, and the low noise, tight-matching of the complementary bi- polar transistors, excellent analog accuracy is achieved. one ad- vantage of the rail-to-rail output amplifiers used in the ad7390/ ad7391 is the wide range of usable supply voltage. the part is fully specified and tested for operation from 1 2.7 v to 1 5.5 v. power supply bypassing and grounding precision analog products, such as the ad7390/ad7391, re- quire a well filtered power source. since the ad7390/ad7391 operates from a single 1 3 v to 1 5 v supply, it seems conve- nient to simply tap into the digital logic power supply. unfortu- nately, the logic supply is often a switch-mode design, which generates noise in the 20 khz to 1 mhz range. in addition, fast logic gates can generate glitches hundred of millivolts in ampli- tude due to wiring resistance and inductance. the power supply noise generated thereby means that special care must be taken to assure that the inherent precision of the dac is maintained. good engineering judgment should be exercised when address- ing the power supply grounding and bypassing of the ad7390.
ad7390/ad7391 rev. 0 C9C the ad7390 should be powered directly from the system power supply. this arrangement, shown in figure 22, employs an lc filter and separate power and ground connections to isolate the analog section from the logic switching transients. 100? elect. 10-22? tant. 0.1? cer. ttl/cmos logic circuits +5v power supply +5v +5v return ferrite bead: 2 turns, fair-rite #2677006301 figure 22. use separate traces to reduce power supply noise whether or not a separate power supply trace is available, how- ever, generous supply bypassing will reduce supply-line induced errors. local supply bypassing consisting of a 10 m f tantalum electrolytic in parallel with a 0.1 m f ceramic capacitor is recom- mended in all applications (figure 23). c +2.7v to +5.5v 0.1 m f v out clr sdi clk ld 1 2 3 4 gnd ref v dd ad7390 or ad7391 * 8 7 6 5 10 m f 1 * optional external reference bypass figure 23. recommended supply bypassing for the ad7390/ad7391 input logic levels all digital inputs are protected with a zener-type esd protec- tion structure (figure 24) that allows logic input voltages to ex- ceed the v dd supply voltage. this feature can be useful if the user is driving one or more of the digital inputs with a 5 v cmos logic input-voltage level while operating the ad7390/ ad7391 on a 1 3 v power supply. if this mode of interface is used, make sure that the v ol of the 5 v cmos meets the v il input requirement of the ad7390/ad7391 operating at 3 v. see figure 10 for a graph for digital logic input threshold versus operating v dd supply voltage. v dd logic in gnd figure 24. equivalent digital input esd protection in order to minimize power dissipation from input-logic levels that are near the v ih and v il logic input voltage specifications, a schmitt trigger design was used that minimizes the input-buffer current consumption compared to traditional cmos input stages. figure 9 shows a plot of incremental input voltage versus supply current showing that negligible current consumption takes place when logic levels are in their quiescent state. the normal crossover current still occurs during logic transitions. a secondary advantage of this schmitt trigger, is the prevention of false triggers that would occur with slow moving logic transi- tions when a standard cmos logic interface or opto isolators are used. the logic inputs sdi, clk, ld , clr all contain the schmitt trigger circuits. digital interface the ad7390/ad7391 have a double-buffered serial data input. the serial-input register is separate from the dac register, which allows preloading of a new data value into the serial regis- ter without disturbing the present dac values. a functional block diagram of the digital section is shown in figure 4, while table i contains the truth table for the control logic inputs. three pins control the serial data input. data at the serial data input (sdi) is clocked into the shift register on the rising edge of clk. data is entered in msb-first format. twelve clock pulses are required to load the 12-bit ad7390 dac value. if additional bits are clocked into the shift register, for example when a microcontroller sends two 8-bit bytes, the msbs are ig- nored (figure 25). the clk pin is only enabled when load ( ld ) is high. the lower resolution 10-bit ad7391 contains a 10-bit shift register. the ad7391 is also loaded msb first with 10 bits of data. again if additional bits are clocked into the shift register, only the last 10 bits clocked in are used. the load pin ( ld ) controls the flow of data from the shift reg- ister to the dac register. after a new value is clocked into the serial-input register, it will be transferred to the dac register by the negative transition of the load pin ( ld ). b15 x x b14 x x b13 x x b12 x x b11 d11 x b10 d!0 x b9 d9 d9 b8 d8 d8 b7 d7 d7 b6 d6 d6 b5 d5 d5 b4 d4 d4 b3 d3 d3 b2 d2 d2 b1 d1 d1 b0 d0 d0 msb lsb lsb byte 0 byte 1 msb d11_d0: 12-bit ad7390 dac value; d9_d0 10-bit ad7391 dac value x = dont care the msb of byte 1 is the first bit that is loaded into the dac figure 25. typical ad7390-microprocessor serial data input forms
ad7390/ad7391 rev. 0 C10C reset ( clr ) pin forcing the clr pin low will set the dac register to all zeros and the dac output voltage will be zero volts. the reset func- tion is useful for setting the dac outputs to zero at power-up or after a power supply interruption. test systems and motor con- trollers are two of many applications which benefit from power- ing up to a known state. the external reset pulse can be generated by the microprocessors power-on reset signal, by an output from the microprocessor, or by an external resistor and capacitor. clr has a schmitt trigger input which results in a clean reset function when using external resistor/capacitor generated pulses. the clr input overrides other logic inputs, specifically ld . however, ld should be set high before clr goes high. if clr is kept low, then the contents of the shift reg- ister will be transferred to the dac register as soon as clr re- turns high. see the control-logic truth table i. unipolar output operation this is the basic mode of operation for the ad7390. as shown in figure 26, the ad7390 has been designed to drive loads as low as 5 k w in parallel with 100 pf. the code table for this op- eration is shown in table iv. +2.7v to +5.5v 0.1 m f v out clr sdi clk ld 3 2 1 4 gnd ref v dd ad7390 7 6 5 10 m f 1 m c rs rl 3 5k w cl 100pf ext ref 0.01 m f r figure 26. ad7390 unipolar output operation table iv. ad7390 unipolar code table hexadecimal decimal output number number voltage (v) in dac register in dac register v ref = 2.5 v fff 4095 2.4994 801 2049 1.2506 800 2048 1.2500 7ff 2047 1.2494 000 0 0 the circuit can be configured with an external reference plus power supply, or powered from a single dedicated regulator or ref- erence depending on the application performance requirements. bipolar output operation although the ad7391 has been designed for single-supply op- eration, the output can be easily configured for bipolar opera- tion. a typical circuit is shown in figure 27. this circuit uses a clean regulated 1 5 v supply for power, which also provides the circuits reference voltage. since the ad7391 output span swings from ground to very near 1 5 v, it is necessary to choose an external amplifier with a common-mode input voltage range that extends to its positive supply rail. the micropower con- sumption op196 has been designed just for this purpose and re- sults in only 50 microamps of maximum current consumption. connection of the equal valued 470 k w resistors results in a dif- ferential amplifier mode of operation with a voltage gain of two, which results in a circuit output span of ten volts, that is, 2 5 v to 1 5 v. as the dac is programmed with zero-code 000 h to midscale 200 h to full-scale 3ff h , the circuit output voltage v o is set at 2 5 v, 0 v and 1 5 v (minus 1 lsb). the output volt- age v o is coded in offset binary according to equation 4. 3 4 equation 4 v o = 3 5 1 2 2 1 512 d where d is the decimal code loaded in the ad7391 dac regis- ter. note that the lsb step size is 10/1024 = 10 mv. this cir- cuit has been optimized for micropower consumption including the 470 k w gain setting resistors, which should have low tem- perature coefficients to maintain accuracy and matching (prefer- ably the same material, such as metal film). if better stability is required the power supply could be substituted with a precision reference voltage such as the low dropout ref195, which can easily supply the circuits 162 m a of current, and still provide additional power for the load connected to v o . the micropower ref195 is guaranteed to source 10 ma output drive current, but only consumes 50 m a internally. if higher resolution is re- quired, the ad7390 can be used with the addition of two more bits of data inserted into the software coding, which would re- sult in a 2.5 mv lsb step size. table v shows examples of nominal output voltages v o provided by the bipolar operation circuit application. digital interface circuitry omitted for clarity op196 bipolar output swing 1 5v 2 5v v o < 50 m a 2 5v 1 ad7391 v out gnd ref v dd c 470k w 470k w 1 5v < 100 m a i sy < 162 m a figure 27. bipolar output operation table v. bipolar code table hexadecimal decimal analog number number output in dac register in dac register voltage (v) 3ff 1023 4.9902 201 513 0.0097 200 512 0.0000 1ff 511 -0.0097 000 0 -5.0000
ad7390/ad7391 rev. 0 C11C microcomputer interfaces the ad7390 serial data input provides an easy interface to a va- riety of single-chip microcomputers ( m cs). many m cs have a built-in serial data capability which can be used for communi- cating with the dac. in cases where no serial port is provided, or it is being used for some other purpose (such as an rs-232 communications interface), the ad7390/ad7391 can easily be addressed in software. twelve data bits are required to load a value into the ad7390. if more than 12 bits are transmitted before the load ld input goes high, the extra (i.e., the most-significant) bits are ignored. this feature is valuable because most m cs only transmit data in 8-bit increments. thus, the m c sends 16 bits to the dac in- stead of 12 bits. the ad7390 will only respond to the last 12 bits clocked into the sdi input, however, so the serial-data interface is not affected. ten data bits are required to load a value into the ad7391. if more than 10 bits are transmitted before load ld returns high, the extra bits are ignored.
ad7390/ad7391 rev. 0 C12C outline dimensions dimensions shown in inches and (mm). printed in u.s.a. 8-lead soic (so-8) 0.1968 (5.00) 0.1890 (4.80) 8 5 4 1 0.2440 (6.20) 0.2284 (5.80) pin 1 0.1574 (4.00) 0.1497 (3.80) 0.0688 (1.75) 0.0532 (1.35) seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) bsc 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45 8-pin plastic dip (n-8) 8 14 5 0.430 (10.92) 0.348 (8.84) 0.280 (7.11) 0.240 (6.10) pin 1 seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 8-pin tssop (ru-8) 8 5 4 1 0.122 (3.10) 0.114 (2.90) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 0.0256 (0.65) bsc seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0 c2151C18C7/96

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